1. Field of the Invention
The present invention relates to a thin film transistor substrate and a manufacturing method thereof, and more particularly, to an amorphous silicon thin film transistor substrate having a gate driver for an LCD panel and a manufacturing method thereof.
2. Description of the Related Art
A liquid crystal display (LCD) is one of the most popular flat panel displays (FPDs). An LCD generally includes two substrates, each having an electrode formed on an inner surface thereof, and a liquid crystal layer interposed between the two substrates. In an LCD, a voltage is applied to the electrode to re-align liquid crystal molecules and control an amount of light transmitted through the liquid crystal layer.
TFT-LCDs are now the most common type of LCDs. Electrodes are formed on each of the two substrates and thin film transistors (TFTs) are used for switching power supplied to each electrode. The TFT is typically formed on one side of the two substrates.
Generally, an LCD in which TFTs are respectively formed in unit pixel regions is classified as an amorphous type TFT-LCD and a polycrystalline type TFT-LCD. The polycrystalline type TFT-LCD has advantages in that it is capable of speedier operation at low power consumption. It has also an advantage in that TFTs for pixels and semiconductor devices for drive-circuits can be formed together.
On the other hand, the driving circuit for the polycrystalline type TFT-LCD further needs an annealing process for transforming an amorphous silicon into polycrystalline silicon after the amorphous silicon is deposited. In other words, in case that a glass substrate is used, a deformation in the glass substrate may occur during the annealing process. Also, since the gate driver has a structure of complementary metal oxide semiconductor (CMOS), both of n-channel transistor and p-channel transistor are formed on the same substrate. Thus, as compared with a manufacturing process of the amorphous type TFT-LCD in which a single channel type transistor is formed, a manufacturing process of the polycrystalline type TFT-LCD is more complicated and difficult.
In general, a substrate on which TFTs for an LCD are formed is manufactured by a photolithography process using a plurality of masks, and five or six photolithography process steps are used. Since the photolithography process is expensive, it is desirable to reduce the number of photolithography steps.
There is provided an LCD panel substrate. In the above LCD panel substrate, a gate pattern includes a gate line formed on a pixel region and a peripheral region of a transparent insulating substrate respectively and a gate electrode branched from the gate line. A gate insulating film is formed on the substrate having the gate pattern. An active pattern is formed on the gate insulating film and includes a first impurity region, a second impurity region, and a channel region formed between the first impurity region and the second impurity region. A data pattern is formed on the active pattern and the gate insulating film. The data pattern includes a first electrode in contact with the first impurity region, a second electrode in contact with the second impurity region and a data line coupled to the first electrode. A first insulating interlayer is formed on the data pattern and the gate insulating film. The first insulating interlayer includes a first contact hole for partially exposing the first electrode, a second contact hole for exposing the gate electrode of a first drive transistor of the peripheral region and a third contact hole for exposing the first/second electrode of a second drive transistor of the peripheral region. An electrode pattern part is formed on the first insulating interlayer. The electrode pattern part includes a first electrode pattern coupled to the first electrode of the pixel region through the first contact hole, and a second electrode pattern connecting the partially exposed gate electrode of the first drive transistor with the exposed first/second electrode of the second drive transistor through the second and third contact holes.
Also, there is provided an LCD panel substrate, in which a gate pattern includes a gate line formed on a pixel region and a peripheral region of a transparent insulating substrate respectively and a gate electrode branched from the gate line. A gate insulating film is formed on the substrate having the gate pattern. An active pattern is formed on the gate insulating film and includes a first impurity region, a second impurity region, and a channel region formed between the first impurity region and the second impurity region. A data pattern is formed on the active pattern and the gate insulating film and includes a first electrode in contact with the first impurity region, a second electrode making contact with the second impurity region and a data line coupled to the first electrode. A first insulating interlayer is formed on the data pattern and the gate insulating film. The first insulating interlayer includes a first contact hole for partially exposing the second electrode, a second contact hole for partially exposing the first electrode of the pixel region, a third contact hole for exposing the gate electrode of a first drive transistor of the peripheral region, and a fourth contact hole for exposing the first/second electrode of a second drive transistor of the peripheral region. An electrode pattern part is formed on the first insulating interlayer. The electrode pattern part includes a first electrode pattern coupled to the second electrode of the pixel region through the first contact hole, a second electrode pattern coupled to the first electrode of the pixel region through the second contact hole, and a third electrode pattern connecting the exposed gate electrode of the first drive transistor with the exposed first/second electrode of the second drive transistor through the third and fourth contact holes.
There is also provided a method for manufacturing an LCD panel substrate. In the above method, a gate pattern including a gate line formed on a pixel region and a peripheral region of a transparent insulating substrate respectively and a gate electrode branched from the gate line are formed. A gate insulating film, a non-doped amorphous silicon layer, an impurity-doped amorphous silicon layer, and a metal layer are formed on the insulating substrate having the gate pattern. A photoresist pattern is formed on the metal layer. Here, a portion the photoresist pattern corresponding to a channel region between a source electrode and a drain electrode is thinner than portions corresponding to the source electrode and the drain electrode. The metal layer, the doped amorphous silicon layer, and the amorphous silicon layer are patterned using the photoresist pattern as a mask to remove the metal layer of the channel region and to form a data pattern including the source electrode, the drain electrode spaced apart from the source electrode, and a data line coupled to the drain electrode and substantially perpendicular to the gate line. The photoresist pattern and the impurity-doped amorphous silicon layer of the channel region are removed. An insulating interlayer is formed on a resultant structure of the substrate. The insulating interlayer is partially etched to form a first contact hole for partially exposing the drain electrode of the pixel region, a second contact hole for exposing the gate electrode of a first transistor of the peripheral region, and a third contact hole for exposing the source/drain electrode of a second transistor of the peripheral region. A conductive film is formed on the first insulating layer having the first, second and third contact holes. The conductive film is patterned to form a first electrode pattern and a second electrode pattern. The first electrode pattern is coupled to the drain electrode of the pixel region through the first contact hole, and the second electrode pattern connects the partially exposed gate electrode of the first transistor with the exposed source/drain electrode of the second transistor through the second and third contact holes.
Also, there is provided a method for manufacturing an LCD panel substrate. In the above method, a gate pattern includes a gate line on a pixel region and a peripheral region of a transparent insulating substrate respectively and a gate electrode branched from the gate line. A gate insulating film, a non-doped amorphous silicon layer, an impurity-doped amorphous silicon layer and a metal layer are sequentially formed on the gate pattern and the substrate. A photoresist pattern is formed on the metal layer. Here, a portion of the photoresist pattern corresponding to a channel region between a source electrode and a drain electrode is thinner than portions corresponding to the source electrode and the drain electrode. The metal layer, the doped amorphous silicon layer and the amorphous silicon layer are patterned using the photoresist pattern as a mask to remove the metal layer of the channel region and to form a data pattern including the source electrode and the drain electrode spaced apart from the source electrode. The photoresist pattern and the impurity-doped amorphous silicon layer of the channel region are removed. A first insulating interlayer is formed on a resultant structure of the substrate. The first insulating interlayer is partially etched to form a first contact hole for partially exposing the drain electrode of the pixel region, a second contact hole for partially exposing the source electrode of the pixel region, a third contact hole for exposing the gate electrode of a first transistor of the peripheral region and a fourth contact hole for exposing the source/drain electrode of a second transistor of the peripheral region. A conductive film is formed on the first insulating interlayer having the first, second, third and fourth contact holes. The conductive film is patterned to form a first electrode pattern, a second electrode pattern and a third electrode pattern. The first electrode pattern is coupled to the source electrode of the pixel region through the first contact hole, the second electrode pattern is coupled to the drain electrode of the pixel region through the second contact hole and the third electrode pattern connects the exposed gate electrode of the first transistor with the exposed source/drain electrode of the second transistor through the third and fourth contact holes.
Further, there is provided a method for manufacturing an LCD panel substrate. In the above method, a gate pattern including a gate line on a pixel region and a peripheral region of a transparent insulating substrate respectively and a gate electrode branched from the gate line are formed. A gate insulating film is formed on the substrate having the gate pattern. An active pattern is formed on the gate insulating film. The active pattern includes a first impurity region, a second impurity region and a channel region between the first impurity region and the second impurity region. A data pattern including a drain electrode placed on and making contact with the first impurity region, a source electrode placed on and in contact with the second impurity region and a data line coupled to the source electrode and substantially perpendicular to the gate line is formed. An insulating interlayer is formed on the data pattern and the gate insulating film. The insulating interlayer is partially etched to form a first contact hole for partially exposing the drain electrode of the pixel region, a second contact hole for exposing the gate electrode of a first drive transistor of the peripheral region and a third contact hole for exposing the source/drain electrode of a second drive transistor of the peripheral region. A conductive film is formed on the insulating interlayer having the first, second and third contact holes. The conductive film is patterned to form a first electrode pattern and a second electrode pattern. The first electrode pattern is coupled to the drain electrode of the pixel region through the first contact hole and the second electrode pattern connecting the exposed gate electrode of the first drive transistor with the exposed source/drain electrode of the second drive transistor through the second and third contact holes.
Furthermore, there is provided a method for manufacturing an LCD panel substrate. In the above method, a gate pattern including a gate line on a pixel region and a peripheral region of a transparent insulating substrate respectively and a gate electrode branched from the gate line is formed. A gate insulating film is formed on the substrate having the gate pattern. An active pattern is formed on the gate insulating film. The active pattern includes a first impurity region, a second impurity region and a channel region between the first impurity region and the second impurity region. A data pattern including a drain electrode placed on and making contact with the first impurity region, a source electrode placed on and making contact with the second impurity region and a data line coupled to the source electrode and substantially perpendicular to the gate line is formed. A first insulating interlayer is formed on the data pattern and the gate insulating film. The first insulating interlayer is partially etched to form a first contact hole for partially exposing the source electrode of the pixel region, a second contact hole for partially exposing the drain electrode of the pixel region, a third contact hole for exposing the gate electrode of a first transistor of the peripheral region and a fourth contact hole for exposing the source/drain electrode of a second transistor of the peripheral region. A conductive film is formed on the first insulating interlayer having the first, second, third and fourth contact holes. The conductive film is patterned to form a first electrode pattern, a second electrode pattern and a third electrode pattern. The first electrode pattern is coupled to the source electrode of the pixel region through the first contact hole, the second electrode pattern being coupled to the drain electrode of the pixel region through the second contact hole and the third electrode pattern connecting the exposed gate electrode of the first transistor with the exposed source/drain electrode of the second transistor through the third and fourth contact holes.
Thus, according to the present invention, an area of the gate driving region is minimized and at the same time the number of the masks used for forming the thin film transistor is decreased to four or five sheets.